Senior ASIC Engineer

2 days ago

Thiruvananthapuram, Kerala, India beBeePhysicalDesign Full time ₹ 1,50,00,000 - ₹ 2,50,00,000

We are seeking an experienced Physical Design Engineer with a strong background in ASIC design.

Job Description

The ideal candidate will have expertise in floor planning, placement, routing, and timing closure. They will be responsible for providing technical guidance, mentoring junior engineers, and interfacing with front-end ASIC teams to resolve issues.

The successful candidate will work on low-power designs using techniques such as voltage islands, power gating, and substrate-bias. They should also have experience with Cadence or Synopsys or Magma physical design tools, as well as scripting languages such as PERL and TCL.

The ideal candidate will have excellent communication skills, both written and oral, and be able to clearly document plans. They should also be able to interface with different teams and prioritize work based on project needs.

  • Top-level floor planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
  • Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
  • Timing closure on DDR2/DDR3/PCIE interfaces.

Requirements:

  • 4-12 years of experience in ASIC Physical Design.
  • Strong background in Cadence or Synopsys or Magma physical design tools.
  • Expertise in scripting languages such as PERL and TCL.
  • Excellent communication skills, both written and oral.
  • Ability to clearly document plans.
  • Ability to interface with different teams and prioritize work based on project needs.

Preferred Skills:

  • Experience with 65nm or lower node designs.
  • Knowledge of static timing analysis in Primetime or Primetime-SI.
  • Strong physical verification skills.

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