High-Level Digital Fault Testing Expert

1 week ago

Amrāvati, Maharashtra, India beBeeDigitalFaultTesting Full time ₹ 15,00,000 - ₹ 25,00,000

Job Role:

Digital Fault Testing Engineer

We are seeking a seasoned professional to join our team as a Digital Fault Testing Engineer. This is a high-level technical position that will work closely with the ASIC design teams to ensure digital fault testing design rules and coverages are met.

The ideal candidate will have extensive experience in generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models through on-chip test compression techniques.

Responsibilities include developing MBIST verification, creating test pattern generation using Mentor tool, and ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations.

The successful candidate will also be responsible for supporting post-silicon debug effort, issue resolution, and diagnostic tool generation for ATPG, MBIST, and bring-up on ATE.

Key Requirements:

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering
  • Minimum of 4 to 12 years' experience in ASIC/DFT - simulation and Silicon validation
  • Should have worked in at least one Full chip DFT
  • Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement
  • In-depth knowledge and hands-on experience in ATPG - coverage analysis
  • In-depth knowledge of Memory verification, repair and failure root-cause analysis
  • Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim
  • Expertise in scripting languages such as Perl, shell, etc. is an added advantage
  • Ability to work in an international team, dynamic environment with good communication skills
  • Ability to learn and adapt to new tools, methodologies
  • Ability to do multi-tasking & work on several high-priority designs in parallel

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