DFT Architect

2 weeks ago

Amrāvati, Maharashtra, India beBeeDigitalFaultTolerance Full time ₹ 20,00,000 - ₹ 30,00,000

Job Title:

Seeking a seasoned Digital Fault Tolerance Expert to develop and implement advanced architectures.

  • Develop and implement cutting-edge DFT architecture with a focus on Memory Built-In Self-Test (MBIST) for System-on-Chip (SoC).
  • Integrate MBIST Intellectual Properties, generate test insertion and verification infrastructure.
  • Lead DFT planning, insertion, simulation, and pattern generation initiatives.
  • Perform Automatic Test Pattern Generation (ATPG) and MBIST pattern generation, debug failures from silicon bring-up.
  • Collaborate with RTL, Physical Design, and Verification teams throughout the design cycle.
  • Support silicon bring-up and yield improvement activities post-silicon.
  • Ensure high coverage and test quality in scan and MBIST.

Requirements:

  • Bachelor's or Master's degree in Electronics or related field.
  • Minimum 7+ years of hands-on experience in DFT with a strong focus on ATPG, SCAN, and MBIST.
  • Proficient in tools such as Synopsys DFT Compiler, Tessent (Mentor), or equivalent.
  • Solid understanding of scan insertion, ATPG, boundary scan, and JTAG.
  • Experience with memory test algorithms, repair analysis, and pattern generation.
  • Familiarity with scripting languages (TCL, Perl, Python) for automation.
  • Strong analytical and problem-solving skills with the ability to work independently.

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