Chip Architect

We are seeking a highly skilled and motivated individual to own the overall chip architecture and design execution.

• Lead multi-block design integration ensuring seamless collaboration among cross-functional teams.
• Manage handoff and sign-off of key stages: RTL freeze, synthesis, place & route, static timing analysis, and DFT to ensure timely completion.
• Drive IP integration, clocking strategy, power domain definition to optimize performance.
• Cross-Functional Collaboration is essential in this role.
• Identify and mitigate design and schedule risks to maintain project momentum.
• Engage with external IP vendors, EDA tool providers to leverage their expertise.

• A strong background in Digital IC design (RTL to GDSII) with a focus on system-level architecture and IP integration.
• Timing closure (STA) and power-performance-area (PPA) optimization to meet demanding product specifications.
• Familiarity with UPF/CPF for low-power design and design for manufacturability, test (DFT), and silicon debug.