Chief DFT Architect
2 days ago
A distinguished DFT architect is required to lead the development of advanced SoC and ASIC designs.
- Define and implement DFT architecture for complex projects, incorporating expertise in scan insertion, compression, ATPG, MBIST, and boundary scan.
Key Responsibilities:
- Develop and manage the DFT flow from RTL to gate-level netlist and silicon bring-up.
- Collaborate with cross-functional teams for seamless integration, including RTL, STA, PD, and test engineering.
- Perform fault simulation, debug, and optimize test coverage gaps.
- Ensure timely delivery of ATE patterns, achieving signoff, timing closure, and yield optimization.
- Mentor junior engineers and develop automation scripts and infrastructure.
Required Skills and Experience:
- Bachelor's or Master's degree in Electronics, Electrical, or VLSI Design.
- 7+ years of experience in DFT for complex ASIC or SoC designs.
- Strong understanding of RTL design, synthesis flows, and scripting languages (Python, Perl, Tcl).
- Expertise in DFT tools such as Synopsys: DFT Compiler, TetraMAX, TestMAX, Siemens EDA: Tessent ScanPro, MBIST, IJTAG, Cadence/others: Modus, Encounter Test.
Preferred Qualifications:
- Experience with hierarchical DFT and low-power DFT methodologies (UPF).
- Exposure to post-silicon validation and failure analysis.
We are offering a competitive compensation package, opportunities for growth and professional development, and collaboration with top-tier engineers and industry leaders. If you're an innovative leader with a passion for DFT architecture, we invite you to apply for this exciting opportunity.
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