
Senior Synthesis and Constraints Expert
23 hours ago
We are seeking a highly skilled Senior Synthesis/Constraints Engineer to lead our digital circuit design and verification efforts.
Key Responsibilities:- Synthesis and timing constraint engineering for block, subsystem, partition, and full-chip designs.
- Expertise in EDA tools such as Cadence Genus & Fishtail.
- Experience with TSMC 3nm / 5nm nodes.
- Hands-on implementation of UPF (Universal Power Format).
- Optimization of synthesis PPA (Power, Performance, Area) and hierarchical partition synthesis.
- Lint and sanity checks for design integrity.
- Timing constraints generation and validation.
- Mandatory scripting skills in Tcl, Perl, and Python.
The ideal candidate will have 8+ years of experience in the field and be proficient in leading-edge technologies.
Requirements:- Strong background in digital circuit design and verification.
- Excellent knowledge of synthesis and timing constraints methodologies.
- Experience with popular EDA tools and scripting languages.
- Ability to work collaboratively as part of a cross-functional team.
Candidates should have a strong passion for innovation and a willingness to learn and adapt to new technologies.
What We Offer:- A challenging and dynamic work environment.
- Ongoing training and professional development opportunities.
- A competitive salary and benefits package.
We look forward to hearing from qualified candidates.
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