
Synthesis and Timing Constraint Specialist
3 days ago
We are seeking a seasoned Synthesis and Timing Constraint Expert to join our team. The ideal candidate will have extensive experience in leading synthesis and timing constraint projects from inception to delivery.
Responsibilities:
- • Design and implement high-performance, low-power digital circuits using advanced EDA tools like Cadence Genus & Fishtail.
- • Collaborate with cross-functional teams to identify and resolve complex synthesis and timing constraint issues.
- • Develop and maintain in-depth knowledge of synthesis and timing constraint best practices, and stay up-to-date with industry trends and advancements.
- • Work closely with design engineers to ensure seamless integration of synthesized designs into the overall system architecture.
Requirements:
- • 8+ years of experience in synthesis and timing constraint engineering.
- • Strong expertise in UPF implementation, synthesis PPA optimization, hierarchical partition synthesis, lint, sanity checks, timing constraints generation, and validation.
- • Proficiency in Tcl, Perl, and Python scripting languages.
- • Experience working with TSMC 3nm/5nm nodes and EDA tools.
Bonus Skills:
- • Knowledge of Node-Agnostic Synthesis and Optimization Techniques.
- • Familiarity with Low-Power Design Methodologies.
- • Experience with High-Level Synthesis (HLS) tools.
Interested Candidates please share your resume for consideration.
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