IP/Subsystem Validation Specialist
2 weeks ago
The role requires proven expertise in verifying complex design blocks at the IP, Sub-system or SoC level using System Verilog/UVM or related technologies.
Key Responsibilities:
- Develop and enhance System Verilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects.
- Collaborate with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture.
- Understand TestBench Architecture and develop expertise in TestBench Verification Components.
- Mentor junior engineers.
PREFERRED SKILLS AND QUALIFICATIONS:
- Proficient in IP or Sub-system level ASIC verification
- Architected and developed complex verification environments and infrastructure, including scripting using Perl, Ruby, Make, or similar.
- Exposure to RTL design, software development, formal verification, or other related domains.
- Experience in UVM TestBench Development for complex designs preferred.
- Experience in RAL is preferred.
BENEFITS OF THE ROLE:
- Foster a culture of innovation and collaboration
- Contribute to the development of cutting-edge verification solutions
- Opportunities for professional growth and development
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