
Chief Verification Strategist
2 days ago
Verification Leadership Opportunity:
We are seeking a highly skilled Principal Design Verification Engineer to lead and contribute to the verification of complex IP blocks or SoC subsystems.
About the Role:
The successful candidate will be responsible for developing test plans, verification strategies, and coverage metrics based on design specifications, building and maintaining constrained-random and directed testbenches using SystemVerilog/UVM, collaborating with architects, designers, and other verification engineers to identify and debug design issues, developing and maintaining verification infrastructure, scripts, and regression systems, performing functional and code coverage analysis, driving closure, providing technical guidance and mentorship to junior team members, and participating in silicon bring-up and post-silicon validation when needed.
- Main Responsibilities:
- Lead and contribute to the verification of complex IP blocks or SoC subsystems.
- Develop test plans, verification strategies, and coverage metrics based on design specifications.
- Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM.
- Collaborate with architects, designers, and other verification engineers to identify and debug design issues.
- Develop and maintain verification infrastructure, scripts, and regression systems.
- Perform functional and code coverage analysis, driving closure.
- Provide technical guidance and mentorship to junior team members.
- Participate in silicon bring-up and post-silicon validation when needed.
Requirements:
- B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
- 8–14 years of hands-on experience in ASIC/SoC verification.
- Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa).
- Solid understanding of verification methodologies, functional coverage, and assertion-based verification.
- Experience in developing and maintaining testbenches from scratch.
- Strong debugging skills and familiarity with waveform viewers like Verdi or DVE.
- Good knowledge of scripting languages (Python, Perl, or TCL) for automation.
- Familiarity with version control and CI/CD systems.
Preferred Qualifications:
- Experience in formal verification or emulation is a plus.
- Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB).
- Prior experience in leading a verification team or acting as a verification lead.
- Exposure to post-silicon bring-up and validation.
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