STA Timing Engineer
3 weeks ago
- Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively.
- Perform static timing analysis setup and sign-off for multi-corner, multi-voltage processes to align with PPA targets, initially at the hierarchical level and subsequently at the top-level, reviewing the timing arcs for the .lib generation.
- Collaborate closely with RTL, DFT, and IP teams to ensure smooth integration and address physical design concerns affecting scan shift and scan capture modes for DFT.
- Identify opportunities to optimize clock skew and insertion delay across various corners and modes.
- Evaluate the clock/reset-domain-crossing (CDC/RDC) issues at the netlisting stage and offer feedback on design fixes or establish waivers if the changes are not feasible.
- Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards.
- Create and refine custom scripts using Tcl, Perl, or Python to enhance workflow efficiency and streamline physical design operations.
- Mentor and support junior physical design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance.
PREFERRED EXPERIENCE:
- Over 8-10+ years of professional experience in constraints generation, synthesis, static timing analysis (STA), and IP-level timing and physical design, with a preference for high-performance SerDes designs.
- Proven ability in timing analysis, convergence, timing ECOs, and .lib generation.
- Experience with STA closure on PHYs & understanding the timing requirements across digital and analog macro interfaces is a plus.
- Proficient in physical design tools such as Synopsys ICC2, Primetime, and the ASIC design flow.
- Skilled in scripting with Tcl, Python, or Perl to automate and streamline physical design tasks.
- Excellent problem-solving, leadership, and communication skills and values team culture.
- Capable of thriving in fast-paced environments and managing multiple projects simultaneously.
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Bengaluru, Karnataka, India Capgemini Engineering Full timeExperience: 5+yearsLocation: BangaloreJob Description:As an STA Engineer, you will be responsible for timing closure and verification of complex ASIC or SoC designs. You will work closely with cross-functional teams including physical design, logic design, and architecture to ensure timing requirements are met across various design stages and process...
