STA - Synthesis Design Engineer 2

1 week ago


Hyderabad, India Advanced Micro Devices (AMD) Full time

Job Description THE ROLE: The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. KEY RESPONSIBILITIES: - Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure - Collaborate with designer and PNR teams to achieve closure. - Execute as per schedule. - Complete quality delivery for synthesis and timing closure. - Debug and resolve technical issues PREFERRED EXPERIENCE: - Experienced in synthesis and timing closure - Good to have experience in LEC, CLP - Have handled blocks with complex designs, high frequency clocks and complex clocking - complete understanding of timing constraints, low power aspects and concepts of DFT - Have debug experience to solve issues. - scripting and automation ACADEMIC CREDENTIALS: - Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering



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