STA Synthesis Engineer
4 days ago
Position Description:
- STA (static timing analysis), Verilog/VHDL, and Synthesis will serve you well on our team.
- Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure.
- Embrace technical challenges with your natural passion to innovate.
- Ability to collaborate effectively with different functional teams and strong written/verbal communication.
- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL transforms.
- Professional experience with ECO implementation, both functional and timing closure.
- Familiarity with simulation, debugging tools, and working closely with DV team.
- Experience with multi-clock and multi-power domain designs.
- Familiarity with DFT insertion, and multi-mode timing constraints.
Position Requirements:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent
- Experience with full-chip static timing analysis through tapeout, gate level simulations, and Functional ECO implementation with Automated flows
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Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. Netlist and constraint sign in checks and validation. Responsible to complete synthesis till final-opt with DFT insertion Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
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Sta & Synthesis Engineer
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Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer. Exp.-3.5+yrs. Job Location- Bangalore. Notice Period- Prefer Immediate joiner or less notice period. - Netlist and constraint sign in checks and validation. - Responsible to complete synthesis till final-opt with DFT insertion - Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low...
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STA & Synthesis Engineer
1 week ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...
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STA & Synthesis Engineer
1 week ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...
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STA & Synthesis Engineer
1 week ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks...
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STA & Synthesis Engineer
5 days ago
Bengaluru, India ACL Digital Full timeLooking for STA & Synthesis Engineer.Exp.-3.5+yrs.Job Location- Bangalore.Notice Period- Prefer Immediate joiner or less notice period.Netlist and constraint sign in checks and validation.Responsible to complete synthesis till final-opt with DFT insertionExperience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power...
