ASIC Design Engineer

1 week ago

Hyderabad Secunderabad, India PerfectVIPs Full time ₹ 6,00,000 - ₹ 12,00,000 per year
Job Description

ASIC Design Engineer (Lead/Senior/Junior RTL Design) Job# VE903 Roles & Responsibilities Define micro architecture from datasheet or requirements document Perform RTL-level design, Synthesis, STA, CDC and Lint for any digital logic Perform module-level verification and lint checking Interact with verification engineers for test plan review, coverage debug Technical Skills Required B.Tech/M.Tech in Electronics/VLSI Engineering with experience of 3-5 years in ASIC Design Strong hands-on experience with Verilog RTL-level design, Synthesis, STA, CDC and Lint Should be able to work independently once the design requirements are specified Knowledge of standard interfaces viz., AXI, AHB, SAS, DDR, PCIe, Flash-Memory, OTN, I2C/SPI is a plus Knowledge of Perl, and EDA tools for LEC, Synthesis is a plus Must have good spoken and written communication skills Collaborate well in a team Lead will manage a team of engineers to perform the above tasks. Experience 2 to 12 Years & above Education BE/ ME/ B.Tech/ M.Tech/ MS Location Bengaluru Ahmedabad Bhubaneswar Noida Hyderabad Pune Onsite in India San Jose, USA

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    Hyderabad, India ACL Digital Full time

    RTL (ASIC) Design Engineer Experience : 1-3 YearsLocation : HyderabadInterested,please share your updated resume to

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    RTL (ASIC) Design Engineer Experience : 1-3 Years Location : Hyderabad Interested,please share your updated resume to

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    Hyderabad, India ACL Digital Full time

    RTL (ASIC) Design Engineer Experience : 1-3 Years Location : Hyderabad Interested,please share your updated resume to

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    Hyderabad, India ACL Digital Full time

    RTL (ASIC) Design Engineer Experience : 1-3 Years Location : Hyderabad Interested,please share your updated resume to

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    hyderabad, India ACL Digital Full time

    RTL (ASIC) Design Engineer Experience : 1-3 Years Location : Hyderabad Interested,please share your updated resume to

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