STA - Synthesis Design Engineer

As an Implementation Engineer at Kinara, a Bay Area-based venture backed company, you will play a crucial role in leading and executing Synthesis and Static Timing Analysis (STA) for complex AI SoC designs with multi-mode and multi-power domain functionalities. Your responsibilities will include: - Conducting Synthesis and STA to ensure the quality and...

Experience in ASIC/SoC Physical Design & STA implementation (Synthesis to GDSII). EDA tools - Synopsys: Design Compiler, ICC2, PrimeTime. Cadence: Innovus, Tempus, TCL, Perl, Python, ShellSTA concepts — setup/hold analysis, OCV/AOCV, SI, & Crosstalk

ASIC RTL Design EngineerJob Description:Exp: 5 to 8 yrsLocation: HyderabadGood knowledge on the digital concepts and ASIC flowExperience in RTL coding is a must.Must have hands on experience with SoC design and integration.Experience in Verilog/System-Verilog is a must.knowledge of AMBA protocols - AXI, AHB, APBBasic knowledge on verificationUnderstanding of...

Expertise in one or more of the following domains:Power Optimization: Experience with low-power design techniques and methodologies, including the use of the Unified Power Format (UPF).Timing Optimization: Proficiency in static timing analysis (STA) and experience with design constraints using the Synopsys Design Constraints (SDC) format.Functional Safety...

Mandatory : Looking for candidates who can join immediately or max in 15 days only apply. Experience : 5 - 8 Years Expertise in one or more of the following domains : - Power Optimization : Experience with low-power design techniques and methodologies, including the use of the Unified Power Format (UPF). - Timing Optimization : Proficiency in...

Expertise in one or more of the following domains:Power Optimization: Experience with low-power design techniques and methodologies, including the use of the Unified Power Format (UPF).Timing Optimization: Proficiency in static timing analysis (STA) and experience with design constraints using the Synopsys Design Constraints (SDC) format.Functional Safety...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world's most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity...

Dear Connections,We are Hiring "RTL Design Engineer"·      Location: Bangalore/Hyderabad·      Experience: 4+ YearsJob Summary :We are looking for highly skilled RTL Design Engineers with proven hands-on experience in at least three end-to-end production-grade projects.The ideal candidate should have a strong foundation in RTL coding...

Required skills:Job Description:Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge.Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of 14nm technode STA analysis, DCD knowledge.Candidate is preferably expert...

7+ years of experience in ASIC/SoC Physical Design and STA implementation. Prior experience in handling complex hierarchical designs and leading block-level or top-level integration.Required Skills & Tools:Strong expertise in ASIC Physical Design flow (Synthesis to GDSII).Hands-on experience with EDA tools such as:Synopsys: Design Compiler, ICC2,...