Senior ASIC RTL Design Engineer

6 days ago


Delhi, India MosChip® Full time
ASIC RTL Design:General knowledge how things work in RTL team and be able to handle basic-to-mid level RTL tasks:RTL design/release flows/infra (LINT, CDC, UPF, IPXACT, CSR …)Good working knowledge in general scripting (Perl, Python, Make ...)Customer methodology/flow ask and complaints. Should be able to take up infra cleanup. Some good examples of infra cleanup:Correctly clean PERL warnings during RTL build to find/fix any poor usage of variablesOwn automated tools driven regressions runs of available tools in alternate modes for RTL-focused buildsVCS compiles with selective, not global-ignore, lint and warning bars on just ckt models, hardIP blocks stand-alone, full RTL-only PHYCleanup of grep or other bars to prevent bad `ifdef usage, naming conventions (extend spyglass or add our own), etc.Creating design build configurations for different modes like ATPG, HWEMUL

Experience Required:Minimum of 5 years of experience in ASIC RTL Design, Microarchitecture.



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