Principal IP Design Engineer
2 weeks ago
Principal / Senior Staff IP Design Engineer: 2 Positions
A US based well-funded product based startup looking for talented ASIC / RTL / Logic Design Engineers.
A US based well-funded product-based startup looking for Highly talented ASIC / RTL / Logic Design Engineers for the following roles.
Principal Interconnect Fabric Microarchitecture & IP Logic Design Engineer
Responsibilities
Creating micro-architecture and detailed design documents for design keeping in mind performance, power, area requirements.
Perform RTL coding for complex design blocks in Verilog.
Function/performance simulation check and debug.
Understanding on Lint/CDC/Synthesis checks, power analysis and LEC check.
Understanding and defining constraints.
Issue and track bug reports from beginning to closure.
Work with the team to deliver quality designs.
Work very closely with verification and back-end team.
Key Qualifications
B.E/M. Tech with 8-12 years of experience in ASIC RTL development.
Solid experience with System Verilog.
Experience with Lint, CDC.
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
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