Principal SoC
2 months ago
A US based well-funded product-based startup looking for Highly talented ASIC / RTL / Logic Design Engineers for the following roles.
Responsibilities
Principal / Senior Staff SoC/Chiplet RTL Integration Designer
Responsibilities include:
- Collaborate with SoC/System architects and IP providers to define the RTL (Register Transfer Level) integration strategy for complex System-on-Chip (SoC)/Chiplet designs.- Integrate IP blocks, including CPUs, GPUs, Accelerators, Memory controllers, and peripheral interfaces, into the SoC RTL design using industry-standard methodologies and tools.- Should be able to write synthesis design constraints at IP, System level.- Develop and maintain the RTL integration flow, including RTL partitioning, hierarchical design methodologies, and top-level integration scripts.- Ensure compliance with design specifications, performance requirements, and quality standards throughout the RTL integration process.- Optimize the SoC RTL design for area, power, and performance goals through careful RTL partitioning, IP configuration, and floor-planning techniques.- Perform RTL linting, CDC (Clock Domain Crossing) analysis, and other design rule checks to identify and resolve integration issues early in the design cycle.- Collaborate with verification engineers to develop and execute RTL integration tests, debug integration-related issues, and ensure functional correctness of the SoC design.- Support physical design implementation activities, including synthesis, and timing closure, by providing guidance on RTL-to-GDS integration requirements.
Skills and Experience:
- Proven experience (8-12+ years) in RTL design and integration for complex SoC designs, preferably in the semiconductor or electronics industry.- Proficiency in RTL coding languages, such as Verilog /SystemVerilog and experience with industry-standard EDA (Electronic Design Automation) tools for RTL integration, Synthesis and Verification.- Strong understanding of computer architecture, digital design principles, and SoC integration concepts, including bus protocols, memory architectures, and peripheral interfaces.- Experience with RTL linting tools, and CDC analysis tools, for ensuring RTL design quality and reliability.- Experience with scripting languages, such as Tcl or Python, for automation of RTL integration tasks and tool flows will be an added benefit.- Good communication and collaboration skills, with the ability to work effectively in a multidisciplinary team environment.
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
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