RTL Design Engineer
2 weeks ago
Micro-architecture development
RTL Design/Coding
Quality checks of the implemented RTL for LINT, CDC and DFT rules and clear documentation of exceptions and waivers.
Synthesis and timing closure
Provide support to SoC Integration, constraint development and timing closure.
Contribute and drive quality/cycle time improvement methodologies as a part of the development process.
Be a team player working across functional teams responsible for development of SoCs from spec to silicon.
What do we expect from you? (Mini Qualifications)
Strong RTL design experience of 1-2 years with ASIC/SoC designs
Experience with Hardware Accelerators for mathematical functions and control peripheral designs will be a plus.
Must have strong multi-clock domain design knowledge and expertise in Clock Domain Crossing (CDC) analysis tools.
Experience in timing constraint development at SoC level and timing analysis is preferred.
RTL Synthesis and LEC experiences are a must have.
Experience with scripting and automation including IPXACT exposure would be an added bonus.
Preferred Skills/ Experience
1-2 years of experience in RTL Design (Specification, Microarchitecture, SoC integration and implementation.
Strong experience with Linting, CDC, Synthesis, Equivalence check and timing checker tools are required.
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