ASIC Design Engineer

10 hours ago


india ACL Digital Full time

ASIC Design Engineer We are seeking a skilledASIC Design Engineerwith a solid background indigital design,RTL coding, andASIC development. The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance ASICs, with a strong focus onSystemVerilogorVHDL. This role will involve taking designs from concept to tape-out, working in a collaborative environment with cross-functional teams, and ensuring that designs meet performance, area, and power requirements.Key Responsibilities: Digital RTL Design:Design and implementhigh-performance RTLusingSystemVerilogorVHDLfor complex ASIC designs. Architecture Development:Contribute to the design and specification ofdigital architecturesand system-level components, includingprocessors,memory controllers, and high-speed interfaces. Synthesis & Optimization:Performlogic synthesis,timing analysis, and optimize forarea,power, andperformance(PPA) during the design process. Design Integration:Integrate and interface complex digital blocks into a cohesivesystem-on-chip (SoC)orASIC. Verification:Collaborate with the verification team to developtestbenches, performfunctional simulation, and ensure correctness and robustness of designs. Timing Closure:Work on timing closure for your designs usingstatic timing analysis (STA)tools and ensure all designs meet required timing constraints. Design for Low Power:Implementlow-power design techniques, such asclock gating,power gating, anddynamic voltage scaling. Collaboration:Work closely with cross-functional teams, includingphysical design,verification,software, andquality assuranceteams, to ensure successful integration and deployment of ASIC designs. Documentation:Produce detailed design documentation, includingdesign specifications,test plans, andsimulation results, and track progress against development milestones. Debugging & Optimization:Use simulation tools and hardware debugging techniques to troubleshoot design issues and improve performance, timing, and power.Required Qualifications: Bachelor’s or Master’s degreeinElectrical Engineering,Computer Engineering, or a related field. 4+ years of hands-on experienceinASIC designand RTL development. Expertise inRTL codingusingSystemVerilogorVHDL. In-depth knowledge ofdigital design principles, includingfinite state machines (FSMs),timing analysis,clocking schemes, andsynchronous design. Familiarity withASIC design flow, includingsynthesis,place and route,timing closure, andpower optimization. Experience withsimulation toolslikeModelSim,VCS, orQuestafor functional verification. Knowledge ofstatic timing analysis (STA)andtiming closuretechniques. Strong understanding ofpower analysisand implementation oflow-power designmethodologies. Experience withhardware debugging tools(e.g.,logic analyzers,oscilloscopes,protocol analyzers) for bringing up prototypes. Excellent communication skills and the ability to collaborate effectively with cross-functional teams.Experience: 4 to 10 Years Location: Bangalore / Hyderabad



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