ASIC Physical Design

Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and...

- Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. - Manage project-specific ASIC development flow setup and maintenance. - Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate...

Hi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...

Education RequirementsB. Tech / M. Tech (ECE)Experience3 to 13 YearsJob LocationHyderabadShiftGeneral (No WFH)Work WeekMonday to FridayHe/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and...

UsWe are a technology consulting company delivering best-in class Chip Design Services.Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.Chip Design ServicesAnalog IP DesignFoundation - OpAmp, BandgapIOs - GPIO, I2C, LVDSClocking - PLLPower - LDOSoC DesignRTL Design, Integration, Lint/CDC/RDC, UPFIP/SoC UVM...

Responsibilities:- Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. - Worked on 65nm or lower node...

He/She should be able to do top-level floor planning, PG Planning, partitioning,placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have...

Physical Design Engineer (Cadence Innovus) – BangaloreExperience: 3+ Years | Notice Period: Immediate to 30 DaysJob Description:Hiring Physical Design Engineers with hands-on experience in Cadence Innovus and low-power design implementation for end-to-end ASIC flow.Key Skills:Floorplanning, Placement, CTS, Routing, Timing ClosureDRC/LVS, Power &...

DIRECT Applicants - may write to Email : Sunil.Chandran@quest-global.com We are recruiting for below roles ASIC Physical Design Principal Engineer RTL2GDS : 15 - 25 Years Senior Technical Architect - SoC (System on Chip) Physical Design : 15 - 25 Years Role Summary: This is a deep technical leadership role focused on architecting and guiding turnkey SoC...

Position: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...