Senior ASIC RTL Designer
2 days ago
Position: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT readiness. - Collaborate with verification teams for test planning, debugging, and coverage closure. - Integrate IPs into top-level SoC and resolve timing and functionality issues. - Support emulation, FPGA prototyping, and silicon bring-up activities with cross-functional teams.
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ASIC RTL Integration Engineer
4 days ago
New Delhi, India Devloit Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Integration Engineer
6 days ago
New Delhi, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Design Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeRTL (ASIC) Design Engineer Experience : 1-3 Years Location : HyderabadInterested,please share your updated resume to janagaradha.n@acldigital.com
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ASIC RTL Design Engineer
3 weeks ago
New Delhi, India ACL Digital Full timeASIC RTL Design Engineer Location : BangaloreJob Description: Skills & Experience: • 3-5 years of experience in ASIC front end design and quality check. • Strong fundamental knowledge of digital design, Verilog, and scripting language. • Experience in multiple clock and voltage domain design. • Working knowledge for FE flows like Lint, CDC,...
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ASIC RTL Integration Engineer
5 days ago
Delhi, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Integration Engineer
6 days ago
Delhi, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC SOC RTL Design Lead
6 days ago
New Delhi, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...
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Senior RTL Design Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeHi All,Job Location: Bangalore,hyderabadNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic...
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SeniorPrincipal ASIC RTL Design Engineer
4 days ago
Delhi, India Proxelera Full timeSummary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing,...
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RTL Design Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 YearsJob DescriptionJob Role: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design...