SeniorPrincipal ASIC RTL Design Engineer
4 days ago
Summary: Own end-to-end RTL design for complex SoC or large subsystem blocks, from micro-architecture through tapeout and silicon bring-up.Responsibilities:Define micro-architecture from specs; write high-quality synthesizable SystemVerilog/Verilog RTL for SoC-level or large subsystems.Own design bring-up, block/subsystem integration, and close on timing, power, and area with synthesis and PnR teams.Drive design reviews, close bugs, and support silicon validation and post-silicon debug.Collaborate with DV to define test plans, assertions, and coverage goals; support emulation/FPGA only as a secondary validation aid (not counted toward the 10 years).Must-have qualifications:10+ years of hands-on ASIC RTL development experience (FPGA work does not count toward the 10 years).Multiple production ASIC tapeouts owning significant SoC or subsystem functionality (e.g., interconnects, coherency, memory subsystem, high-speed I/O, security, or power-management islands).Strong SystemVerilog/Verilog RTL and micro-architecture skills, including clock/reset design, low-power techniques (UPF/retention/isolation), and AMBA/standard bus protocols (AXI/ACE/AHB/APB).Proven collaboration with physical design on synthesis constraints, timing closure, DFT hooks, and ECOs.Proven silicon bring-up experience for owned blocks/subsystems.Nice to have:Exposure to coherency protocols, cache/memory controllers, DDR/PCIe subsystems, security/crypto blocks.SVA for design-level assertions, performance modeling, or power/perf analysis skills.Scripting for design productivity (Tcl/Python), used in service of hands-on RTL work.
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Senior ASIC RTL Designer
2 days ago
New Delhi, India Eximietas Design Full timePosition: ASIC RTL Design EngineerLocation: Bangalore / HyderabadExperience: 6+ years- Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and...
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ASIC RTL Integration Engineer
5 days ago
Delhi, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Integration Engineer
6 days ago
Delhi, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Integration Engineer
4 days ago
New Delhi, India Devloit Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC RTL Integration Engineer
5 days ago
New Delhi, India DevloiT Full timePosition: ASIC RTL Integration / ASIC RTL CodingLocation: Bangalore, IndiaEmployment Type: Long Term ContractMinimum Experience: 4 Years+About the Role:We are seeking a skilled ASIC RTL Integration Engineer with hands-on experience in developing and integrating RTL for IPs or subsystems. The ideal candidate should have a deep understanding of architectural...
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ASIC SOC RTL Design Lead
6 days ago
New Delhi, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...
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ASIC RTL Design Engineer
4 weeks ago
New Delhi, India ACL Digital Full timeRTL (ASIC) Design Engineer Experience : 1-3 Years Location : HyderabadInterested,please share your updated resume to janagaradha.n@acldigital.com
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ASIC RTL Design Engineer
3 weeks ago
New Delhi, India ACL Digital Full timeASIC RTL Design Engineer Location : BangaloreJob Description: Skills & Experience: • 3-5 years of experience in ASIC front end design and quality check. • Strong fundamental knowledge of digital design, Verilog, and scripting language. • Experience in multiple clock and voltage domain design. • Working knowledge for FE flows like Lint, CDC,...
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RTL Design Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeRTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 1 to 3 YearsJob DescriptionJob Role: Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design...
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RTL Design Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeRTL Design Engineer (ASIC)Location: Chennai, Tamil NaduExperience: 1 to 3 YearsJob DescriptionJob Role:- Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. - Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. - Integrate complex subsystems into SoC environments and support...
