SOC DFT Engineer

Job DescriptionWe are looking for an energetic, passionate and process oriented DFT Engineers who has extensive experience in planning, implementation and verification of DFT features for multiple SoC.Direct Responsibilities of the role, but not limited to,working on various aspects of IP and SoC DFT including the DFT Architecture, Spyglass DFT, RTL...

L&T Technology is hiring for Senior DFT Engineers / Lead DFT Engineer with 8-15 Years of experience. Job Location : Bangalore Skills Expertise should be : ATPG, SOC, ASIC DFT.

Job Description-The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these.The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations,...

SoC DFT EngineerJob Description:Scan insertion.SCAN DRC/Coverage debug.ATPG Pattern generation.Gate level simulations ( Zero delay/Timing Delay simulations).Worked on JTAG/P1500 protocols.Perl/Tcl scripting.Timing/Formal verification/PD flow knowledge is plus.Location: BangaloreNotice Period: ImmediateExperience: 5+ Years

Experience: 4+yearsLocation: BangaloreJob DescriptionWill be responsible for Designing and Implementing DFT techniques.Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.Test Modes implementation and verification, scan...

Role : DFT Engineer.Location : Bangalore (work from office).Experience : 5+ years.Job Description : We are looking for an energetic, passionate and process oriented DFT Engineers who has extensive experience in planning, implementation and verification of DFT features for multiple SoC. Direct Responsibilities of the role, but not limited to : ...

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSIExperience: 5 - 25 yearsWork Location: Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation: Engineering (excluding Mechanical/Civil)Detailed JD:5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one Full chip DFT...

Job Title:Lead DFT EngineerLocation:BengaluruExperience:12+ YearsNotice Period: 30daysRole OverviewWe are seeking an experiencedLead DFT Engineerto drive the integration and optimization ofDesign-for-Test (DFT) architecturein our LiDAR SoCs. In this role, you will own DFT strategy, planning, implementation, and validation across our high-performance silicon...

Job Title:Lead DFT EngineerExperience:7+ YearsLocation:BangaloreEmployment Type:Full-timeIndustry:Semiconductors / ASIC / SoC DesignJob Summary:We are looking for aLead DFT Engineerto drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional...

Design for Testability (DFT) Engineer (Senior Level - 10+ years’ experience)Job Summary:We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...