Senior DFT Engineer

Purpose:The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor technology...

Hi All,Greetings from Eximietas!Position: Senior DFT Engineers/Leads/Architects.Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). An intimate knowledge and experience in scan chain...

DFT EngineerLocation: BangaloreNotice Period: 30 daysJob Description:We are looking for a skilled DFT Engineer with 3–5 years of experience in ASIC design and verification with a strong focus on Design-for-Test methodologies. You will be responsible for implementing and verifying DFT architectures to ensure high test coverage and manufacturability.Key...

DescriptionWe are seeking talented and motivated individuals to join our team in developing cutting-edge solutions with Application-Specific Microcontrollers (MCUs) for the rapidly evolving automotive industry. Our MCUs power a wide range of critical vehicle functions, including traction control, onboard charging (OBC) and DC-DC converters, advanced lighting...

Experience: 10–15 YearsWe are looking for a highly experienced DFT Engineer with strong expertise in Mentor Graphics Tessent tools. The candidate should have deep hands-on experience across the full DFT flow—implementation, validation, debug—and be able to work independently on complex SoC designs.Key ResponsibilitiesPerform RTL insertion, DFT DRC...

Job responsibilities:Implement scan insertion, ATPG pattern generation, Memory and logic bist implementationPerform DFT simulations and analyze results to ensure test coverage and quality.Debug and resolve DFT-related issues throughout the design process.Job qualification:Senior DFT engineer with 4+ years of experience in SoC DfT implementation and...

Purpose of the Role:The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor...

L&T Technology is looking to hire for DFT Engineer Job Location : Bangalore Skills should be : Scan insertion, ATPG, JTAG, test Kompress and scripting

Job DescriptionLead complete DFT architecture, planning, and implementation for advanced SoC designs.Develop and integrate scan chains, MBIST/LBIST, boundary scan (JTAG IEEE 1149.1/1500), and compression logic.Generate ATPG patterns, perform coverage analysis, and drive defect reduction and yield improvement.Work on RTL/gate-level DFT insertion, constraints...

Job Requirements Job Title: Senior DFT Lead EngineerJob Type: Full-Time We are currently seeking a Senior DFT Lead Engineer with expertise in SCAN, ATPG, and BIST. As the ideal candidate, you will be responsible for leading the DFT efforts within our team, ensuring the successful implementation of design-for-test methodologies. Your role will involve...