Clocks Validation

Functional Validation with Python scriptingLocation: BangaloreJob Description:Good at SoC topicsReset conceptsClock conceptsMultiple COM protocolsPython scriptingStrong in C and C++, linkers, memory organization, resource partition and handlingAdded advantage of Perspec(Cadence Flow)Good at Silicon DebugExperience (years) : 3-8 yearsEducation...

Job Description:MSEE/BSEE with 8+ years in chip validation.Experience with PCIe Gen5/6 designs and its Silicon validation is requiredExperience in planning the Si validation process and creating realistic schedule estimates.Strong experience in high level Object Oriented with C/C++, System Verilog is mustExperience with debug of SW drivers, HW designs and FW...

Key Responsibilities:Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies.Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies.Collaborate cross-functionally with RTL, physical design,...

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the...

General Summary:Job Summary:8-14 years of experience in Performance Validation (preferably AI/ML workloads) on complex CPU/GPU/NPU chipsets/IPsQDSP team is responsible for delivering high-performance NSP (neural signal processor) cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space.Qualcomm is the largest fabless design...

Experiencce - 2.5 EXPLocation - Noida* Block level Timing Constraints enablement & analysis ;* Clocking & Data flow understanding ;* Well versed in reviewing check_timing and Constraints QoR checks + Constraints Validation understanding ;* Able to interact with Implementation team counterparts for block timing closure ;* CTS building understanding along with...

Title-Principal/Staff SerDes Design EngineerExp-10+Loc-BangaloreJob SummarySeeking an experienced SerDes Design Engineer to develop next-generation high-performance wireline transceivers in advanced nodes. The role involves designing high-speed AMS circuits for SerDes PHY (TX, RX, CDR, PLL, biasing, clocking) with industry-leading power, performance, and...

Key Responsibilities:• Perform electrical characterization of interfaces (e.g., CAN, LIN,SAR-ADC, DS-ADC, Flex-ray , USB, SPI, I²C, DDR, Ethernet).• Validate power, clock, reset, and peripheral functionality across operating conditions (voltage, temperature).• Measure signal integrity, power sequencing, voltage drops, and current consumption using...

*Job Area:*Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:Job DescriptionResponsibilities will includeTo be strong designer who is able to work independent on one of the peripheral IPscome up with design and microarchitecture solutionsguide/mentor juniorsengage with external teams to drive/resolve cross team dependencies.Take...

Job Description:Own RTL design of SoC-level or large subsystems from specification to silicon bring-up.Define and implement micro-architecture; write high-quality, synthesizable RTL in SystemVerilog/Verilog.Work closely with physical design teams for synthesis, timing closure, power, area optimization, DFT hooks, and ECOs.Drive block/subsystem integration...