SoC DV Clocking

5 days ago

Bengaluru, Karnataka, India Quest Global Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Job Requirements

Key Responsibilities
  • Develop and execute the end-to-end verification strategy for the entire SoC clocking and reset subsystem.
  • Architect and build a comprehensive, reusable UVM-based testbench to verify complex clocking features.
  • Verify the functionality of critical clocking components, including Phase-Locked Loops (PLLs), clock generators, glitchless clock multiplexers, and configurable clock dividers.
  • Create and debug complex test sequences to validate all aspects of clock control, including register programming, dynamic frequency scaling (DFS), and various clocking modes.
  • Implement and execute a robust power-aware verification strategy using UPF, with a strong focus on verifying clock gating functionality across the chip.
  • Own the Gate-Level Simulation (GLS) plan for the clocking domain to catch timing-related bugs and ensure post-synthesis design correctness.
  • Collaborate closely with Architecture, RTL Design, and Physical Design teams to identify verification challenges, debug complex issues, and achieve functional sign-off.
  • Drive coverage closure by defining and tracking relevant functional and code coverage metrics.
Required Qualifications
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of hands-on experience in ASIC/SoC Design Verification.
  • Direct and extensive experience in verifying complex clocking and reset subsystems for large-scale SoCs.
  • Strong proficiency in verification methodologies, particularly UVM and SystemVerilog.
  • Proven experience in developing complex testbenches, verification components, and constrained-random test scenarios from scratch.
  • Solid understanding of SoC architecture, including bus protocols and CPU interactions.
Preferred Qualifications
  • Demonstrable experience with low-power verification methodologies and the Unified Power Format (UPF).
  • Deep understanding of Gate-Level Simulation (GLS), including setup and debug.
  • Strong knowledge of PLL functionality, clock jitter, and glitch-free clock switching concepts.
  • Proficiency in scripting languages such as Python, Perl, or Tcl for automation and data analysis.
  • Experience debugging issues that span hardware, firmware, and software.
  • Prior experience working in a fast-paced, collaborative, large-scale project environment.

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