Staff Physical Design Validation Engineer

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You are an accomplished engineer with a passion for physical design and validation, eager to make a tangible impact on advanced semiconductor products. You thrive in dynamic environments and relish the challenge of solving complex problems with innovative thinking and technical prowess. Your expertise spans chip-level floor planning, bus/pin planning, clock tree synthesis, placement, optimization, routing, and signoff processes. You bring a strong foundation in scripting, utilizing Python, Perl, or Tcl to automate and enhance design flows. You are comfortable working with block and SOC-level RTL-GDS2 flows and have a proven track record in delivering high-quality silicon on time. You are adept at both independent problem-solving and collaborative teamwork, able to communicate effectively with cross-functional teams and stakeholders. Your knowledge of low-power checks, timing closure, and signoff methodologies ensures robust and reliable designs. You are always learning, staying up to date with the latest tools and techniques in the industry, and you approach every challenge with resilience, curiosity, and a commitment to excellence. Whether mentoring junior engineers or driving technical discussions, you lead by example, fostering an inclusive and innovative team environment.

• Lead and manage physical design activities for large and cutting-edge chip projects, ensuring high quality and timely delivery.
• Execute chip-level floor planning, bus/pin planning, clock tree synthesis, placement, optimization, routing, and parasitic extraction.
• Perform static timing analysis, IR drop analysis, physical verification, and signoff for robust and reliable silicon.
• Develop, maintain, and enhance physical design flows using advanced scripting techniques to improve efficiency and accuracy.
• Collaborate with cross-functional teams to resolve technical challenges, debug complex issues, and drive solutions for significant design problems.
• Contribute to block/SOC-level timing closure and low-power design checks, applying industry best practices and innovative methodologies.

• Enable delivery of high-performance, reliable chips powering next-generation applications in AI, automotive, networking, and consumer electronics.
• Advance Synopsys' leadership in physical design innovation by contributing to state-of-the-art methodologies and tools.
• Streamline design flows, reducing time-to-market and increasing project efficiency through automation and scripting.
• Mentor and guide junior team members, elevating technical expertise and fostering a collaborative culture.
• Ensure robust signoff and verification, minimizing risks and maximizing product quality for Synopsys customers.
• Drive technical excellence and continuous improvement, positioning Synopsys at the forefront of semiconductor design.

• BS or MS in Electrical Engineering, Computer Engineering, or related field; specialization in VLSI is preferred.
• 5+ years of hands-on experience in physical design, with expertise in block/SOC-level RTL-GDS2 flows.
• Strong scripting skills in Python, Perl, Tcl, or Shell for flow automation and debugging.
• Comprehensive understanding of signoff methodologies, including timing closure, power planning, and verification checks (MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM).
• Familiarity with Synopsys and Cadence EDA tools for advanced physical design and validation.

• Analytical, detail-oriented, and proactive in addressing complex technical challenges.
• Collaborative team player with excellent communication skills, able to work with diverse teams and stakeholders.
• Innovative and adaptable, embracing new tools and methodologies for continuous improvement.
• Resilient and goal-driven, capable of delivering high-quality results under tight deadlines.
• Supportive mentor and open-minded learner, committed to knowledge sharing and team development.

You'll join a world-class physical design validation team in Bangalore, working alongside experts in architecture, verification, and EDA tool development. The team is dedicated to pushing the boundaries of silicon performance and reliability, delivering industry-leading solutions for global clients and fostering a collaborative, innovative environment.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.