Memory layout design lead
2 weeks ago
Memory Layout Lead – Best-in-Class Semiconductor Memory IPs
As a Memory Layout Lead, you will drive the physical design and delivery of high-performance, low-power, and high-density semiconductor memory IPs (SRAM, ROM, register files, CAMs, and more). You will own the complete layout strategy—from bitcell integration to periphery circuits—ensuring best-in-class PPA (performance, power, area) and yield, while meeting strict foundry rules.
Key Responsibilities
• Lead end-to-end layout design and floorplanning for advanced-node memory IPs.
• Deliver DRC/LVS/DFM-clean GDS with robust EM/IR reliability sign-off.
• Collaborate with circuit, CAD, and SoC integration teams for optimal implementation.
• Innovate layout techniques to achieve competitive density and performance targets.
• Provide comprehensive IP deliverables: GDSII, LEF, Liberty (.lib), Verilog models, and integration documentation.
Success Metrics
• Achieves world-class memory density and access times.
• Meets or exceeds power and yield requirements across PVT corners.
• Enables seamless integration into customer SoCs.
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