Memory Layout Engineer
2 days ago
Key Responsibilities:
Perform custom layout design of high-performance and low-power memory blocks (SRAM, ROM, Register Files, CAM, etc.).
Work on floorplanning, transistor-level layout, device matching, and parasitic optimization.
Ensure DRC/LVS clean layouts with adherence to foundry design rules.
Collaborate with circuit design teams to achieve optimal PPA (Performance, Power, Area).
Conduct parasitic extraction, EM/IR analysis, and reliability checks for memory layouts.
Deliver high-quality layouts meeting project deadlines and silicon success.
Required Skills:
Strong expertise in memory layout (SRAM, ROM, CAM, Register Files).
Hands-on experience with Cadence Virtuoso, Mentor Calibre, Synopsys tools.
Deep knowledge of foundry design rules (DRC, LVS, ERC, ANT, etc.).
Familiarity with advanced process nodes (7nm/5nm/3nm preferred).
Strong understanding of layout-dependent effects (LDE), electromigration, IR drop.
Good communication and ability to work in cross-functional teams.
Good to Have:
Experience with automation scripts (Perl/Python/Tcl) for layout productivity.
Knowledge of EDA flow development for memory layout.
Experience in custom analog layout is a plus.
Education:
B.E/B.Tech/M.Tech in Electronics, Electrical, VLSI, or related field.
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