Memory Layout Engineer

21 hours ago

Bengaluru, Karnataka, India UANDWE, Inc. Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Memory Layout

Role: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.

Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories.

Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required

Experience : 2 to 8Years

Above 1 year

Understanding of memory architecture

Experience in creating basic memory layouts from scratch

Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers

Knowledge of compiler issues

Understanding of reliability issues

Simulation effects

EMI (Electromagnetic Interference) considerations

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