Memory Layout Engineer
7 days ago
Experience Level 3 to 8 Years ( Mid-Level Role)
Responsibilities:
As Memory Layout Engineer, we will work on developing memory compilers layouts and memory Fast Cache instances layouts for our next generation Cores achieving outstanding PPA.
Required Skills and Experience :
We Prefer graduate or postgraduate from a University or Engineering School, in Electronic Engineering or equivalent Engineering Degree.
- We expect you to have basic understanding of CMOS Transistors, their behaviors.
- We expect some basic understanding of CMOS logic design and layout.
- Understanding of Power versus Performance versus Area trade-offs in typical CMOS design.
- You have an engineering demeanor and Passion for Circuit layouts.
- Expected to have good interpersonal skills.
- Capable of creating high quality design rule driven layout
- Able to review schematics with engineering and propose changes based on layout implications.
- Exploring possible floor planning options and proposing improvements
- Minimum 5Yrs of experience in SRAM / memory layouts creation and backend verifications including EMIR analysis.
Nice To Have Skills and Experience :
- You know basic scripting languages, e.g. Perl/skill.
- Some Experience of working on Cadence or Synopsys flows.
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