Memory Layout Engineer
1 week ago
Required Skills & Tools:
- Strong experience in Custom Layout design using tools such as Cadence Virtuoso, Synopsys Custom Compiler, or Mentor Pyxis.
- Good knowledge of semiconductor devices, transistor-level design, and layout techniques for high-density memory cells.
- Familiarity with DRC/LVS tools (Calibre, Pegasus, ICV).
- Understanding of technology nodes (e.g., 28nm, 16nm, 7nm FinFET, etc.).
- Scripting knowledge in Skill, Perl, or Python is a plus for layout automation.
- Knowledge of EDA flow integration, reliability checks (EM/IR), and layout vs. schematic correlation.
Job Type: Full-time
Pay: ₹863, ₹2,556,813.59 per year
Work Location: In person
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