STA CAD Engineer, Senior

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Minimum Qualifications:• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Job Title: STA CAD EngineerLocation: BangaloreDepartment: GCADJob Type: Full-TimeExperience Level: 2-4 years Job Summary:We are seeking a highly motivated STA CAD Engineer to join our CAD/EDA team. The ideal candidate will be responsible for developing, maintaining, and supporting Static Timing Analysis (STA) flows and methodologies across multiple technology nodes and design platforms.This role involves close collaboration with design, methodology, and EDA tool teams to ensure robust, scalable, and efficient timing signoff solutions. Key Responsibilities:Develop and maintain STA flows using industry-standard tools (e.g., PrimeTime, Tempus).Automate and optimize timing analysis flows for performance, runtime, and scalability.Collaborate with design teams to define timing constraints and validate timing closure methodologies.Support timing signoff activities across multiple projects and technology nodes.Interface with EDA vendors to evaluate and integrate new tool features and enhancements.Debug complex timing issues and provide root cause analysis and solutions.Develop and maintain documentation, training materials, and best practices.Drive innovation in timing analysis through scripting, machine learning, or advanced analytics. Required Qualifications:Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.Strong understanding of STA concepts, timing constraints (SDC), and timing closure methodologies.Proficiency in scripting languages such as Tcl, Python, or Perl.Experience with EDA tools like PrimeTime, Tempus, or similar.Familiarity with digital design flow, synthesis, place & route, and signoff.Excellent problem-solving, debugging, and communication skills. Preferred Qualifications:Experience with CAD infrastructure development and flow integration.Knowledge of advanced timing techniques (e.g., ECO timing closure, hierarchical STA, MCMM).Exposure to cloud-based or distributed compute environments.Experience with version control systems (e.g., Git, Perforce).Prior experience in a CAD/Methodology team supporting large SoC designs. Applicants: Qualcomm is an equal opportunity employer. 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