STA Engineer
2 days ago
Job Title: STA (Static Timing Analysis) Engineer – VLSI
Location: Bangalore (Only)
Experience: 4 – 10 Years
Immediate Joiners Only
Job Description
We are looking for an experienced STA VLSI Engineer to join our growing semiconductor team in Bangalore. The ideal candidate should have strong expertise in Static Timing Analysis across advanced technology nodes and hands-on experience with industry-standard EDA tools.
Key Responsibilities
Perform full-chip and block-level Static Timing Analysis (STA)
Setup and analyze timing constraints (SDC) including clocks, I/O constraints, exceptions
Perform timing closure for different modes and corners (MCMM)
Identify and debug setup, hold, recovery, and removal violations
Work closely with PD, RTL, and synthesis teams to resolve timing issues
Analyze timing reports and provide optimization recommendations
Handle ECOs related to timing fixes
Support signoff STA including LVF/CCS, OCV/AOCV/POCV
Required Skills & Qualifications
4 to 10 years of hands-on experience in STA for VLSI designs
Strong understanding of timing concepts, clocking, CDC basics
Expertise in PrimeTime / Tempus tools
Good experience with SDC, ECO flows, and timing signoff
Knowledge of advanced nodes (7nm/10nm/16nm/28nm) is a plus
Familiarity with low-power design techniques (UPF/CPF)
Good analytical and debugging skills
Strong communication and teamwork abilities
Skills: timing,static timing analysis,sta
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