Physical Design Engineer

Company DescriptionCambio Consulting Pvt Ltd, established in 2005, is a leading Recruitment Consulting Firm based in Bangalore and Hyderabad. Known for being a strategic staffing partner, the firm has successfully placed over 5000 employees across various verticals, such as Cloud, Virtualization, Big Data, Analytics, ERP, Networking, Storage, Hardware,...

Company Description:MosChip Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions with over 1300 engineers based in Silicon Valley, USA, and India. With expertise spanning end-to-end silicon design, verification, systems, software, and device engineering, MosChip offers comprehensive solutions including...

Job Requirements Job Title: Lead Physical Design EngineerWe are currently seeking a highly skilled Lead Physical Design Engineer to join our team on a temporary basis. As the Lead Physical Design Engineer, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex integrated circuits. Key...

Job Requirements Job Title: Lead Physical Design Engineer We are currently seeking a highly skilled Lead Physical Design Engineer to join our team on a temporary basis. As the Lead Physical Design Engineer, you will be responsible for overseeing the physical design process, ensuring the successful implementation of complex integrated circuits. Key...

Role Description:This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products.Qualifications:He/She should be able to do...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning(for hierarchical designs),placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks,...

What You'll Be Doing : In this position, you will expect to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification.Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design...

Technical RequirementsExcellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.In-depth knowledge of floor planning, power planning, PNR and signoff checksStrong experience in static timing analysis (STA), timing closure, and signal integrity.Expertise in power optimization...

Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Worked on 65nm or lower node...

Responsibilities:Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...