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Physical Design Engineer

2 weeks ago

Hyderabad, Telangana, India MosChip® Full time ₹ 4,00,000 - ₹ 8,00,000 per year

Company Description:

MosChip Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions with over 1300 engineers based in Silicon Valley, USA, and India. With expertise spanning end-to-end silicon design, verification, systems, software, and device engineering, MosChip offers comprehensive solutions including multimedia, mobility, connectivity, AI/ML solution design, and test automation. The company has a proven track record with millions of connectivity ICs developed and 200+ successful SoC tape-outs of first-time right silicon.

Role Description:

This is a full-time on-site role for a Physical Design Engineer located in Hyderabad. The Physical Design Engineer will handle various tasks such as physical design, physical verification, logic design, circuit design, and RTL design. The role involves working closely with cross-functional teams to ensure seamless integration and functionality of designs.

Qualifications:

  • He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, 
    design
     rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
  • Minimum of 3-12 years of experience in SOC 
    Physical
     
    design
    .
  • He/She should have worked on 7nm or lower node 
    design
    s with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
  • Provide technical guidance, mentoring to 
    physical
     
    design
     engrs.
  • Lead a team of 
    Physical
     
    design
     
    engineer
    s and be responsible 
    for
     their blocks' closure
  • Interface with front-end ASIC teams to resolve issues.
  • Low Power 
    Design
     - Voltage Islands, Power Gating, Substrate-bias techniques.
  • Expertise in Timing closure on high speed interfaces is a plus
  • Excellent communication skills.
  • Strong Back ground of ASIC 
    Physical
     
    Design
    : Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
  • Extensive experience and detailed knowledge in Cadence or Synopsys.
  • Expertise in scripting languages such as PERL, TCL.
  • Strong 
    Physical
     Verification skill set.
  • Static Timing Analysis in Primetime or Primetime-SI.
  • Good written and oral communication skills. Ability to clearly document plans.
  • Ability to interface with different teams and prioritize work based on project needs.