Senior Physical Design Engineer

Physical Design Engineer - Senior / Lead Job Description: Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization. Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing closure, and physical design sign-off. Physical Design: Experience in...

Senior / Lead Physical Design Engineer - EMIR Job Description: Good understanding of IR/Power-Domain-Network signoff at SOC & block level. Experience in RHSC tool. Good at scripting – python. Must have knowledge of Physical Implementation (Synthesis and Place & Route). Effective communication. Strong analytical and problem solving abilities. EMIR signoff...

WHAT YOU DO AT AMD CHANGES EVERYTHINGWe care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our...

Technical Requirements- Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.- In-depth knowledge of floor planning, power planning, PNR and signoff checks- Strong experience in static timing analysis (STA), timing closure, and signal integrity.- Expertise in power...

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power...

Technical RequirementsExcellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.In-depth knowledge of floor planning, power planning, PNR and signoff checksStrong experience in static timing analysis (STA), timing closure, and signal integrity.Expertise in power optimization...

Responsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Worked on 65nm or lower node...

Company Overview : MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defence, Consumer Electronics, Automotive, Medical and Networking & Telecommunications. Job Description: Experience: 4 - 12 Years Location:...

and RequirementsAt Synopsys we re at the heart of the innovations that change the way we work and play Self-driving cars Artificial Intelligence The cloud 5G The Internet of Things These breakthroughs are ushering in the Era of Smart Everything And we re powering it all with the world s most advanced technologies for chip design and software...

What You'll Be Doing : In this position, you will expect to lead all block/chip level PD activities. PD activities includes floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification.Work in collaboration with design team for addressing design challenges. Help team members in debugging tool/design...