Rtl Design Engineer

Job Description

We are looking for a passionate RTL Design Engineer to design and implement complex logic for our indigenous SoCs and IPs. The role involves working across the full front-end design cycle, from specification to silicon bring-up, while collaborating closely with cross-functional teams.

Key Responsibilities

• Define micro-architecture and develop high-quality Verilog RTL code for SoC blocks and IPs. - Implement and integrate standard bus protocols such as AXI, AHB, APB, and custom interconnects. - Develop and maintain detailed documentation for logic designs, including specifications and micro-architecture details. - Collaborate with Design Verification (DV) and Physical Design (PD) teams to ensure clean integration and closure of bugs/issues. - Debug verification and synthesis-related issues, apply ECO fixes when necessary. - Contribute to lint, CDC, RDC, and synthesis constraint checks for sign-off quality RTL. - Support post-silicon bring-up, root cause analysis of issues, and propose design workarounds or fixes. - Work with architects to explore and prototype new design methodologies and optimizations.

Required Qualifications & Experience

• B.E./B.Tech/M.E./M.Tech in EE/ECE with 35 years of experience in digital design. - Strong expertise in HDL coding (Verilog; VHDL/SystemVerilog a plus). - Hands-on experience in designing digital IP blocks and SoC components. - Solid understanding and practical experience with bus protocols (AXI, AHB, APB, Wishbone, etc.). - Familiarity with synthesis, linting, CDC/RDC, STA constraints, and timing closure flows. - Exposure to DFT concepts and power-aware design is a plus. - Knowledge of scripting languages (Python, Perl, Tcl, Shell) to automate design tasks. - Good exposure to verification environments and ability to work closely with DV teams.

Soft Skills

• Strong analytical, mathematical, and problem-solving skills. - Effective written and verbal communication. - Start-up mentality: fast-paced, flexible, and collaborative.

• Self-driven, curious, and comfortable working on open-ended design challenges. - Ability to work under ambiguity and with flexible schedules.

Perks and Benefits

• Work with world-class engineers and experience a steep learning curve. - Competitive salary with equity options for deserving candidates. - Flexibility to work remotely. - Comprehensive medical coverage for you and your family (100% covered). - Lunch and travel expense reimbursement.

• Senior RTL Design Engineer

Job Description

We are seeking a highly skilled Senior RTL Design Engineer to take ownership of complex SoC/IP designs, drive architecture discussions, and provide technical leadership across the RTL design lifecycle. This role requires expertise in bus protocols, deep VLSI front-end design experience, and the ability to mentor junior engineers while collaborating with verification, physical design, and architecture teams.

Key Responsibilities

• Lead micro-architecture definition and RTL design for high-performance, low-power SoC/IP blocks. - Architect, implement, and integrate advanced bus/interconnect protocols (AXI4, ACE, CHI, AHB, APB, PCIe, etc.). - Own design quality through lint/CDC/RDC checks, synthesis readiness, and timing closure. - Collaborate with DV teams to define verification strategies, review test plans, and ensure high coverage. - Partner with PD teams to achieve timing, power, and area goals at advanced technology nodes (7nm/5nm/3nm). - Debug complex pre-silicon and post-silicon issues, propose root-cause solutions, and drive ECOs. - Provide technical mentorship and guidance to junior RTL designers. - Participate in architectural exploration, performance analysis, and IP integration planning. - Contribute to continuous improvement of design methodologies and automation scripts.

Required Qualifications & Experience

• B.E./B.Tech/M.E./M.Tech in EE/ECE with 7+ years of experience in RTL design. - Proven track record in delivering production-quality RTL for complex SoCs and IPs. - Deep expertise in Verilog/SystemVerilog; familiarity with VHDL is a plus. - Strong knowledge of bus protocols (AXI4, AHB, APB, CHI, PCIe, etc.) and interconnect architectures. - Hands-on experience with synthesis, static timing analysis (STA), and power-performance optimization.

• Familiarity with DFT, low-power design (UPF/CPF), and advanced verification methodologies. - Proficiency in scripting (Python, Perl, Tcl, Shell) to enhance design automation. - Strong debug and problem-solving skills across RTL, gate-level, and silicon bring-up stages.

Soft Skills

• Excellent communication and technical leadership skills. - Ability to mentor and guide a team of junior engineers. - Strong analytical, problem-solving, and decision-making abilities. - Collaborative mindset with experience working in cross-functional teams. - Ability to thrive in a fast-paced, startup-like environment.

Perks and Benefits

• Opportunity to lead and deliver cutting-edge SoC/IP designs. - Competitive salary with attractive equity options. - Flexibility for remote/hybrid work.