RTL Design Engineer

7 days ago


Remote, India Spar Business Services Private LimitedJOBJABS Full time ₹ 20,00,000 - ₹ 25,00,000 per year

JD:

Logic design and integration

Code microarchitecture

SystemVerilog

Experience with FlexNoc - huge plus

FPGA prototyping - huge plus

Job Type: Full-time

Pay: ₹2,000, ₹2,500,000.00 per year

Experience:

  • SystemVerilog: 5 years (Preferred)
  • RTL: 5 years (Preferred)
  • FPGA: 5 years (Preferred)
  • Micro Structure: 5 years (Preferred)

Work Location: Remote


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