Lead Physical design Engineer

Lead ASIC Physical Design ExpertWe are seeking a seasoned Lead ASIC Physical Design expert to join our team. In this pivotal role, you will be responsible for leading the design of complex IP/SoC in advanced process technologies, catering to global semiconductor clients.Key Responsibilities:Oversee the physical design of complex ASIC projects from Netlist to...

Job Role:We are seeking a seasoned expert in physical design to assume a leadership position within our organization.Key Responsibilities:Create detailed physical designs from RTL/Netlist to GDSII, ensuring seamless integration and optimal performance.Ensure the successful completion of physical, timing & power signoff at the block level.Develop and...

Senior / Lead Physical Design Engineer - EMIR Job Description: Good understanding of IR/Power-Domain-Network signoff at SOC & block level. Experience in RHSC tool. Good at scripting – python. Must have knowledge of Physical Implementation (Synthesis and Place & Route). Effective communication. Strong analytical and problem solving abilities. EMIR signoff...

Technical Requirements- Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team.- In-depth knowledge of floor planning, power planning, PNR and signoff checks- Strong experience in static timing analysis (STA), timing closure, and signal integrity.- Expertise in power...

Physical Design Engineer - Senior / Lead Job Description: Strong background in digital IC design, including floorplanning, placement, routing, clock tree synthesis, and optimization. Tools Expertise: Proficient in Innovus, ICC2, and Fusion Compiler for place and route, timing closure, and physical design sign-off. Physical Design: Experience in...

Technical Requirements Excellent problem-solving, leadership, and communication skills. Ability to work in a fast-paced environment and lead a cross-functional team. In-depth knowledge of floor planning, power planning, PNR and signoff checks Strong experience in static timing analysis (STA), timing closure, and signal integrity. Expertise in power...

*Job Area:*Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize,...

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning(for hierarchical designs),placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks,...

We are seeking an experienced ASIC Physical Design Expert to lead complex projects from netlist to GDSII.Key Responsibilities:Drive the physical design process, ensuring timely delivery and optimal performance.Collaborate with engineers to develop innovative designs, leveraging industry-standard EDA tools.Develop and maintain expertise in timing closure...

We are seeking a highly skilled Physical Design Engineer to join our team in the development of cutting-edge System-on-Chip (SoC) designs.As a key member of our engineering team, you will be responsible for designing and implementing complex SoC physical design solutions using industry-leading tools and technologies.Responsibilities:PnR tool expertise in...