Physical Design Engineer, Lead

7 days ago

Hyderabad, Telangana, India Qualcomm Full time ₹ 12,00,000 - ₹ 36,00,000 per year

*Job Area:*Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Minimum Qualifications:Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space.Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification.Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forwardWork closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA)Tabulate metrics results for analysis comparisonDevelop Place & Route recipes for optimal PPAMinimum Qualifications7+ years of High Performance core Place & Route and ASIC design Implementation work experiencePreferred QualificationsExtensive experience in Place & Route with FC or Innovus is an absolute mustComplete ASIC flow with low power, performance and area optimization techniquesExperience with STA using Primetime and/or Tempus is requiredProficient in constraint generation and validationExperience of multiple power domain implementation with complex UPF/CPF definition requiredFormal verification experience (Formality/Conformal)Perl/Tcl, Python, C++ skills are neededStrong problem solving and ASIC development/debugging skillsExperience with CPU micro-architecture and their critical pathLow power implementation techniques experienceHigh speed CPU implementationClock Tree Implementation Techniques for High Speed Design Implementation are requiredExposure to Constraint management tool and Verilog coding experience

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