Senior Physical Design Engineer

1 day ago

Hyderabad, Telangana, India MosChip® Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Company Description:

MosChip Technologies is a publicly traded company specializing in Silicon and Product Engineering solutions, boasting over 1300 engineers in Silicon Valley, USA, and India. The company's expertise includes end-to-end silicon design, verification, systems, software, and device engineering, multimedia, mobility, connectivity, AI/ML solution design, and test automation. MosChip excels in the development of Digital IPs, Verification IPs, Mixed Signal IPs, and Turnkey ASIC services. Over the years, MosChip has successfully developed and shipped millions of connectivity ICs and delivered 200+ SoC tape-outs with first-time right silicon.

Role Description:

This is a full-time, on-site role located in Hyderabad for a Senior Physical Design Engineer. The Senior Physical Design Engineer will be responsible for executing physical design, verification tasks, and logic, circuit, and RTL design activities. Daily tasks include collaborating with cross-functional teams to implement and verify design specifications, optimizing design performance, and ensuring design robustness and manufacturability. The engineer will also provide technical guidance and mentorship to junior team members.

Qualifications:

  • He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
  • Minimum of 3-12 years of experience in physical design.
  • He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
  • Provide technical guidance, mentoring to physical design engrs.
  • Lead a team of Physical design engineers and be responsible for their blocks' closure
  • Interface with front-end ASIC teams to resolve issues.
  • Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques.
  • Expertise in Timing closure on high speed interfaces is a plus
  • Excellent communication skills.
  • Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure.
  • Extensive experience and detailed knowledge in Cadence or Synopsys.
  • Expertise in scripting languages such as PERL, TCL.
  • Strong Physical Verification skill set.
  • Static Timing Analysis in Primetime or Primetime-SI.
  • Good written and oral communication skills. Ability to clearly document plans.
  • Ability to interface with different teams and prioritize work based on project needs.

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