Physical Design Lead

Overview:

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Responsibilities:

SMTS SILICON DESIGN ENGINEER

THE ROLE:

A Physical Design Engineer role in our IP development team, where a large number of IPs vital for AMD are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. As a hands-on Physical Design Engineer, you will help bridge the gap between IP Design/FEINT and SOC PD team.

THE PERSON:

An experienced Physical Design Engineer with strong records and hands-on Physical Design tools and flows and timing closure. A technical expert who demonstrated strong capability in PD methodology and workflow, anticipating/analyzing/resolving technical and planning issues, and enjoyed interacting with team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

KEY RESPONSIBLITIES:

• Physical Design Engineer who works closely with the SoC PD team for the IP delivered by the IP team and helps bridge the gap between IP Design/FEINT and the SoC PD team.
• Help with the IP timing closure with the SoC PD team, suggesting relevant PnR changes for the IP, and providing feedback to the design teams.
• Manage IP PD support with the SoC team, coordinate the resolution of IP PD and timing closure issues with the SoC teams.
• Collaborating with project management and other team leads on PD deliverables to the project milestones and on quality metrics.

PREFERRED EXPERIENCE:

• Expert in PnR tools and flows
• Good knowledge of timing closure techniques.
• Solid understanding Physical Design tools and flows
• Experience in high-speed designs
• Highly committed to meeting project milestones with high-quality timing constraint delivery
• Experienced in complex SoC full-chip timing floorplanning and timing quality checks
• Ability to work independently on complex tasks
• Knowledge of current sub-micro technologies
• Experience in timing closure

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering with 12+ years of PD experience

Location: Hyderabad India

Qualifications:

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.