Memory Circuit Design Engineer

21 hours ago

Hyderabad, Telangana, India Acesoft Labs Full time ₹ 6,00,000 - ₹ 18,00,000 per year
:

Job Title: Memory Circuit Design Verification Engineer

Memory Circuit Design Verification Engineer

Description

As a Memory Circuit Design Verification Engineer, you will work in a highly innovative, motivated, young and dynamic design team capable of verifying complete products using state of the art memory technologies. You will need to have the ability to evaluate full chip and/or block level functionality and provide solutions to help the timely delivery of a functionally correct design.

Unique Opportunities

Complete ownership of verification and end to end analysis of complex full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that are capable of operating at high speeds of up to 6400MT/s.

Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design.

Work on cross functional tasks that can widen your skill set.

Responsibilities

Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.

Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.

Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.

Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.

Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.

Core Requirements

Basic understanding of CMOS and gate level circuit designs

Familiarity with SPICE

Familiarity with Verilog simulations

Good communication skills and ability to work well in a team

Preferred Qualities

Analytical capability for complex gate level circuit designs

Experience in SystemVerilog, PLI coding

Experience in UVM Test Bench

Experience in DRAM, SRAM or other memory related fields

Experience in AMS verification and co-sim

Experience Level 3-7+ years

Education

Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

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