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Analog Mixed Signal Verification Engineer

2 weeks ago

Noida, Uttar Pradesh, India Synopsys Inc Full time ₹ 9,00,000 - ₹ 12,00,000 per year

Job Description:

We are seeking an experienced Mixed Signal Verification Engineer to join our team. The successful candidate will be responsible for developing and executing verification plans for mixed-signal Designs, collaborating with design and verification teams, and ensuring that our products meet the highest standards of quality and reliability.

Key Responsibilities:

1. Develop and execute verification plans for mixed-signal Design

2. Create testbenches and test cases using languages like SystemVerilog, VHDL, or Verilog

3. Collaborate with design and verification teams to identify and fix issues

4. Develop and maintain verification IP and testbench components

5. Ensure coverage and compliance with industry standards

Requirements:

1. Experience with mixed-signal verification

2. Proficiency in languages like SystemVerilog, VHDL, or Verilog

3. Familiarity with simulation tools like Cadence, Synopsys, or Mentor

4. Strong understanding of digital and analog design principles

5. Excellent problem-solving and communication skills

Skills:

1. Mixed-signal verification

2. SystemVerilog

3. VHDL or Verilog

4. Simulation tools

5. Digital and analog design principles