Lead Verification Engineer

3 days ago


Noida, Uttar Pradesh, India beBeeVerification Full time ₹ 15,00,000 - ₹ 28,00,000
System Verilog UVM Verification Engineer

We are seeking an experienced System Verilog UVM verification engineer to join our team.

  • Develop and implement functional verification plans for complex IP designs.
  • Collaborate with cross-functional teams to define and develop verification requirements.
  • Design and architect SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs.
About the Role:

This is a key position in our verification team, and we are looking for a skilled engineer who can drive innovation and excellence in system verification.

Key Responsibilities:
  • Architect and build SystemVerilog UVM-based verification environments.
  • Develop and execute verification plans to ensure comprehensive coverage of real designs.
  • Debug and resolve issues in verification environments to ensure robust and reliable verification processes.
Requirements:
  • B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience.
  • Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs.
  • Proficiency in writing scripts using Perl, Python, and Shell scripting.
Preferred Qualifications:
  • Experience with high-performance computing and data center systems.
  • Familiarity with mobile and client devices.
  • Knowledge of automotive systems and IoT applications.
Benefits:

We offer a competitive salary and benefits package, as well as opportunities for professional growth and development.



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