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ASIC Verification Engineer Lead
2 weeks ago
Job Title: ASIC Verification Engineer - Lead
Description:
We are seeking a highly skilled ASIC Verification Engineer to lead our verification team. The ideal candidate will have a strong background in digital design and verification, with experience in leading cross-functional teams.
Responsibilities:
- Identify verification environment requirements from specifications, design functionality, and interfaces.
- Develop and verify complex UVM verification environments.
- Evaluate and exercise various aspects of the development flow, including Verilog/SystemVerilog development, functional simulation, constraint development, test planning, behavioral modeling, and verification coverage metrics.
- Collaborate with architects, designers, and VIP teams to accomplish tasks.
- Identify design problems, possible corrective actions, and/or inconsistencies on documented functionality.
- Work with peers to improve methodologies and execution efficiency.
- Adhere to quality standards and good test and verification practices.
- Work as a lead, mentor junior engineers, and help them debug complex problems.
- Able to support customer issues by reproduction and analysis.
- Multitask between different activities.
Qualifications:
- Proven desire to learn and explore new state-of-the-art technologies.
- Demonstrate good written and spoken English communication skills.
- Demonstrate good review and problem-solving skills.
- Knowledgeable with Verilog, VHDL, and/or SystemVerilog.
- Familiarity with scripting languages (BASH/TCSH/PERL/PYTHON/TCL) is a plus.
- Understanding of verification methodology such as UVM.
- Good organization and communication skills.
- Be a solution provider.
- 8+ years of relevant experience.
