Power Optimization

1 week ago

Bengaluru Karnataka, India Advanced Micro Devices, Inc Full time

Overview:
**WHAT YOU DO AT AMD CHANGES EVERYTHING**

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

**Responsibilities**:
**MTS SILICON DESIGN ENGINEER**

**THE ROLE**:
Power is a more and more hot topic in IC design. We are a power/performance/area optimization methodology team. In this position, you will work with global team especially physical design team for GPU chips** physical design power optimization/reduction**. Focus on physical design methodology optimization/update to improve chip Power and Performance/Area (PPA), including RTL -> Syn ->place&route iteration/optimizing. The individual is expected to be an expert in physical design areas, it is a plus to have strong ability in multiple aspects in Front-End or RTL coding experience or Synthesis. The individual is expected know back-end power optimization very well, be very familiar with physical design power reduction methodology, not limited to PD but also can be Frond-end power reduction method.

**THE PERSON**:
Strong self-motivation for technical topics, quick and deep learner, strong communication skill within global engineering team, strong team spirit to help and support team members.

**KEY RESPONSIBILITIES**:

- Develop state-of-art physical design power optimization methodologies.
- Verify and test the power optimization methodology in physical design flow.
- Closely co-work with GPU chip project design team, help/support/drive them to adopt the power optimization methodologies

**PREFERRED EXPERIENCE**:

- More than 3 years of experience in physical design in digital ASIC chips. Preferred 8+ years or more years of experience
- Be very familiar with physical design power optimization methodology, (eg. Clock-gating, power-gating, activity aware PnR, power friendly floorplan, DVFS, multibit re-banking de-bandking, scan path power)
- Expert in Back-End (physical design) EDA tools, especially the power calculation/optimization tools,
- strong flow develop and custom script develop abilities
- Knowledgeable in all aspects of deep submicron ASIC design flow
- Successfully gone through several complete product development cycles
- work well with cross-functional teams
- Good listening, writing and speaking English

**ACADEMIC CREDENTIALS**:

- Masters degree in computer engineering/Electrical Engineering

LI-NS1

Qualifications:

- Benefits offered are described: _AMD benefits at a glance.

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