Static Timing Analysis Sta
22 hours ago
**Description**:
**PreLayout STA (Constraints generation and validation)**
**PostLayout STA (Timing Closure)**
**very good in TCL Scripting.**
**Job description**:
Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).
Develop and maintain methodology and flows related to timing verification and closure.
Generation of block and full chip timing constraints.
Work closely with various multi-functional teams on resolving complex timing issues for major building blocks of complex SoCs.
Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools.
Experiences in : Post Layout / Pre Layout / STA (Timing Closure) / TCL Scripting / SoC / ECO / RTL:
CTC:
Exp CTC:
Notice Period:
Current Location:
Relocation to Bangalore:
LWD:
Offer in Hand:
**Thanks & Regards,**
**Rajesh**
**Salary**: ₹313,452.16 per year
**Benefits**:
- Health insurance
Schedule:
- Monday to Friday
**Experience**:
- total work: 6 years (preferred)
Ability to Commute:
- AECS Layout, Bengaluru, Karnataka (required)
Ability to Relocate:
- AECS Layout, Bengaluru, Karnataka: Relocate with an employer provided relocation package (required)
Work Location: In person
**Speak with the employer**
+91 9030101111
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