Fullchip Synthesis

Experience- 4 to 8 years RTL to Netlist Synthesis experience in Genus and Design compiler is a basic requirement. Meet all the DC/Genus exit criteria including PPA meeting and constrains validation Floorplan based Synthesis knowledge like DCG etc is must Working with RTL designer on constraints debug and feedback on constant basis is must. Prelayout timing...

Job OverviewWe are seeking an experienced SMTS Silicon Design Engineer to join our team. The successful candidate will be responsible for delivering the physical design of tiles and FullChip for next-generation processors.Key ResponsibilitiesHandling RTL to GDS2 flowFloor-plan and Physical Implementation of Power-planSynthesis, Placement, CTS, Routing,...

Experience- 4 to 8 yearsRTL to Netlist Synthesis experience in Genus and Design compiler is a basic requirement.Meet all the DC/Genus exit criteria including PPA meeting and constrains validationFloorplan based Synthesis knowledge like DCG etc is mustWorking with RTL designer on constraints debug and feedback on constant basis is must.Prelayout timing...

STA Lead with expertise in timing constraints handling for different fullchip IO protocol (I2C, DDR, USB etc ) - Generating ECO for timing closure for complex multi power domain designs - Good experience in running STA regression with high number of modes/corners efficiently. - Power recovery with STA signoff - Debug constraint issues in P&R environment -...

Job title: ASIC Engineer - Physical design Experience: 2+ Years What you’ll do: Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO...

Job title: ASIC Engineer - Physical designExperience: 2+ YearsWhat you’ll do:Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing...

Job title: ASIC Engineer - Physical designExperience: 2+ YearsWhat you’ll do:Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing...

Job title: ASIC Engineer - Physical design Experience: 2+ Years What you’ll do: - Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks...

Key skills with hand on:Physical design Engineer, floor planning, Routing, Placement ,CTS, Synthesis ,Timing analysis/Timing Closure,Fullchip,Netlist2GDSII, ICC ,Fusion Compiler, ICV, Calibre ,ICC2, Primetime,PT-PxExperience:5 - 25 yearsWork Location:Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation:Engineering (excluding Mechanical/Civil)Detailed...

Key skills with hand on: Physical design Engineer, floor planning, Routing, Placement ,CTS, Synthesis ,Timing analysis/Timing Closure,Fullchip,Netlist2GDSII, ICC ,Fusion Compiler, ICV, Calibre ,ICC2, Primetime,PT-Px Experience: 5 - 25 years Work Location: Trivandrum, Bangalore, Hyderabad, Chennai, Pune Education: Engineering (excluding Mechanical/Civil)...