Fullchip Synthesis

2 weeks ago

Bangalore City Bengaluru Karnataka, India Xanika Infotech Full time

**Role: Full chip Synthesis**

**work mode: onsite**

**EXP: 7+ Years**

**Location: Bangalore, Koramangala**

**Interview:1st round virtual,2nd round f2f**
- Perform full-chip synthesis using industry-standard tools (e.g., Synopsys Design Compiler, Cadence Genus).
- Develop, refine, and validate SDC constraints for functional and test modes at top-level.
- Optimize for timing, area, power, and DFT requirements during synthesis.
- Collaborate with RTL designers to resolve design issues, improve quality of results (QoR), and meet timing targets.
- Integrate block-level netlists into full-chip synthesis flow.
- Debug and resolve synthesis issues related to constraints, logic equivalence, and library mismatches.
- Perform multi-mode, multi-corner (MMMC) analysis during synthesis to meet sign-off targets.
- Run logic equivalence checks (LEC) between RTL and synthesized netlist.
- Generate and maintain synthesis scripts for reproducible flows using Tcl/Perl/Python.
- Work closely with STA, P&R, and DFT teams for smooth design handover and timing closure.

**Job Types**: Full-time, Permanent

Pay: ₹2,500,000.00 per year

Application Question(s):

- Are you willing to attend F2F for 2nd round of interview?
- Are you an immediate joiner?

**Experience**:

- full-chip synthesis: 8 years (required)
- SDC constraints: 8 years (required)
- Integrate block-level netlists: 8 years (required)
- multi-mode, multi-corner (MMMC) analysis : 8 years (required)
- logic equivalence checks (LEC): 8 years (required)

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